Semiconductor memory, such as a random access memory (RAM), is an essential semiconductor device. A RAM device allows the user to execute both read and write operations on its memory cells. DRAM is a specific category of RAM containing an array of individual memory cells. DRAM devices are commonly used with computers and computer systems. Typically, each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the select device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 100. Each cell 100 contains a storage capacitor 104 and an access field effect transistor (FET) 102. For each cell, one side of the storage capacitor 104 is connected to a reference voltage (illustrated as a ground potential). The other side of the storage capacitor 104 is connected to the drain of the transistor device 102. The gate of the transistor device 102 is connected to a word line 108. The source of the transistor device 102 is connected to a bit line 106 (also known as a digit line). With the memory cell 100 components connected in this manner, the word line 108 controls access to the storage capacitor 104 by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the bit line 106 to be written to or read from the storage capacitor 104. Thus, each cell 100 may contain one bit of data (i.e., a “0” or “1”).
As DRAM devices continue to physically shrink in size, it is difficult to provide capacitors in a small area with sufficient capacitance, typically greater than 20 femtoFarads (fF), in the case of a stacked capacitor DRAM cell. In addition, it is difficult to provide an access transistor with good off-state leakage characteristics for refresh operations and good on-state characteristics to write into the cell. Several designs have been proposed to address these issues
One such design is a silicon-on-insulator (SOI) based memory cell that eliminates the need for a capacitor. See, H. Wann et al., “A Capacitorless DRAM Cell on SOI Substrate,” Tech. Digest, Int'l Electron Device Mtg., pp. 635-638, December 1993; P. Fazan et al., “Capacitor-less 1-T DRAM,” 2002 IEEE Int'l. SOI Conf., pp. 10-13, October 2002; K. Inoh et al., “FBC (Floating Body Cell) for Embedded DRAM on SOI,” 2003 Symp. on VLSI Tech. Digest, June 2003. Such references discuss one-transistor capacitor-less (1T/0C) DRAM cells and the operation of a DRAM circuit employing such cells.
Such capacitor-less cells, however, can suffer from poor performance characteristics related to retention time, access time, distribution characteristics, and reliability. In a 1T/0C DRAM cell, carriers are generated in the substrate bulk to write a “1,” and are pulled out from the substrate bulk to write a “0.” In a 1T/0C DRAM cell employing a planar SOI device, carrier generation can present problems. For example, when impact ionization is essential for operation of such a DRAM cell, device reliability can be poor and efficiency can be reduced at higher temperatures due to a decrease in ionization rate and, therefore, quantum yield. Also, a planar device can result in limited operations that consume power because the transistor must be in an on-state. Further, when the planar SOI devices are physically reduced in size, charge storage can be limited due to the reduced active area.